1. Field of the Invention
The present invention relates to electrically programmable and erasable, nonvolatile memory, and more particularly to such memory based on charge trapping memory cells.
2. Description of Related Art
Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as EEPROM and flash memory are used in a variety of modern applications. A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names NROM, SONOS, and PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.
Conventional SONOS devices use ultra-thin bottom oxide, e.g. less than 3 nanometers, and a bias arrangement that causes direct tunneling for channel erase. Although the erase speed is fast using this technique, the charge retention is poor due to the charge leakage through ultra-thin bottom oxide.
NROM devices use a relatively thick bottom oxide, e.g. greater than 3 nanometers, and typically about 5 to 9 nanometers, to prevent charge loss. Instead of direct tunneling, band-to-band tunneling induced hot hole injection BTBTHH can be used to erase the cell. However, the hot hole injection causes oxide damage, leading to charge loss in the high threshold cell and charge gain in the low threshold cell. Moreover, the erase time must be increased gradually during program and erase cycling due to the hard-to-erase accumulation of charge in the charge trapping structure. This accumulation of charge occurs because the hole injection point and electron injection point do not coincide with each other, and some electrons remain after the erase pulse. In addition, during the sector erase of an NROM flash memory device, the erase speed for each cell is different because of process variations (such as channel length variation). This difference in erase speed results in a large threshold voltage Vt distribution of the erase state, where some of the cells become hard to erase and some of them are over-erased. Thus the target Vt window is closed after many program and erase cycles and poor endurance is observed. This phenomenon will become more serious when the technology keeps scaling down.
One limitation on the size of traditional memory cells arises from the use of diffusion lines in semiconductor substrates for source and drain terminals. The diffusion of impurities used to form the diffusion lines spreads out slightly beyond the locations in which the implant is made, increasing the size of the diffusion region, and making it difficult to shrink to smaller and smaller minimum dimensions, and causing other limitations on cell size, including minimum channel lengths for prevention of punch-through.
One approach to overcoming the problems with use of diffusion lines has been developed bases on induction of conductive inversion regions in the substrate using control electrodes adjacent to the charge storage structure in the memory cell, which act as source and drain terminals. Because there are no implants, the dimensions of the inversion regions can be more precisely controlled according to the minimum feature sizes of the manufacturing process. See, Sasago et al., “90-nm-node multi-level AG-AND type flash memory with cell size of true 2F2/bit and programming throughput of 10 MB/s,” IEDM, 2003, pages 823–826 and United States Patent Application Publication No. US 2004/0084714 by Ishii et al. However, practical implementations of inversion bit line based memory devices have not been reported in the literature, based on charge trapping memory cells.